1. Field of the Invention
The present invention relates to a processor using a pipeline processing. More particularly, it relates to a technique of effecting an access to a register in a one-chip processor which carries out high speed operation processings.
2. Description of the Related Art
Recently, processors have been required to have a higher performance and a lower cost. As a processing system for obtaining higher performance, a pipeline processing is known. In this connection, processors which can execute most of the instructions in one cycle using pipeline processing are on the market. On the other hand, to realize the lower cost, it is essential to reduce the scale of circuit, i.e., the chip size.
However, where pipeline processing is adopted for higher performance, a problem occurs in that it is necessary to provide a port for effecting an access to a register, for each of the pipeline stages, and thus, the scale of circuit of the register becomes large. Also, when the scale of circuit of the register becomes large, further problems arise in that the chip size accordingly becomes large, and the wiring length becomes longer, thereby resulting in an increase in the signal propagation delay on the wiring. Time for the access to the register is one of the critical paths for determining the operational speed of the chip. Accordingly, where the time for the access to the register becomes longer, there is a possibility in that the chip cannot exhibit maximum performance.
In view of the above problems, it has been required, without lowering the performance of the pipeline processing, to decrease the number of ports for accessing the register so as to reduce the scale of circuit, and to realize a high speed operation of the chip.
Note, the problems in the prior art will be explained later in detail in contrast with the preferred embodiments of the present invention.